A bipolar transistor formed with an emitter, collector, and intervening base is typically created in a vertical arrangement along a major surface, referred to here (for convenience) as the upper surface, of a monocrystalline semiconductor body. The emitter, collector, and base are all situated in the semiconductor body. The emitter adjoins the body's upper surface.
The base consists of an intrinsic part (commonly referred to as the "intrinsic base") and one or more laterally adjoining extrinsic parts (commonly referred to as "extrinsic bases"). The intrinsic base lies directly below the emitter. In a standard symmetrical configuration, there are two extrinsic bases located on opposite sides of the intrinsic base. Each extrinsic base includes a heavily doped contact zone which extends to the upper semiconductor surface and to which electrical contact is made at a location spaced laterally apart from the emitter. Each extrinsic base may include a connection (or link) zone that provides a low-resistance electrical path between the intrinsic base and the associated base contact zone.
The collector contains a buried main portion situated below the intrinsic base so that the emitter-collector current flows generally in the vertical direction. The main collector portion extends laterally beyond the intrinsic base to a heavily doped collector contact zone which typically extends to the upper semiconductor surface to provide electrical access to the collector at a location spaced laterally apart from the emitter and the two base contact zones. Overlying ohmic electrical contacts to the emitter and contact zones complete the transistor.
Referring to the drawings, FIG. 1 illustrates a prior art oxide-isolated npn transistor of the vertical type as described in De Jong et al, U.S. Pat. No. 5,006,476. The semiconductor body in FIG. 1 consists of p- monocrystalline silicon substrate 10 and overlying n- epitaxial silicon layer 12. Recessed field-oxide region 14 divides the epitaxial silicon into a group of laterally separated active semiconductor regions, two of which are interconnected by n+ buried layer 16 situated along the metallurgical interface between substrate 10 and epitaxial layer 12.
In the device of FIG. 1, n+ emitter 18, which is formed by dopant outdiffusion from n+ polycrystalline silicon ("polysilicon") emitter contact 20 so as to be self-aligned to emitter contact 20, overlies p intrinsic base 22. The transistor has two extrinsic bases, each formed with a p+ contact zone 24 and a p connection zone 26. N+ collector contact zone 28 connects to a main collector portion consisting of n+ buried layer 16 and overlying n-type epitaxial portions 30 and 32. Metal silicide caps 34, 36, and 38 respectively overlie contact zones 20, 24, and 28. Oxide spacers 40 provide spacing between emitter contact 20 and each metal silicide cap 36 through which a metal line (not shown) is connected to underlying base contact zone 24.
Numerous engineering trade-offs are made in designing vertical bipolar transistors. For example, by incorporating spacers 40 into the npn transistor of FIG. 1, the probability of an electrical short between emitter contact 20 and either of the base contacts is typically quite low. Base connection zones 26 accompany spacers 40 in order to provide low-resistance links between intrinsic base 22 and each base contact zone 24. However, forming connection zones 26 typically entails additional processing and thus additional manufacturing expense.
As the lateral dimensions of transistors shrink, the probability that heavily doped base contact zones 24 will encroach on emitter 22 increases. Tang et al, "Design Considerations of High Performance Narrow-Emitter Bipolar Transistors," IEEE Elect. Dev. Lett., April 1987, pp. 174-175, and Lu, "Lateral Encroachment of Extrinsic-Base Dopant in Submicrometer Bipolar Transistors, " IEEE Elect Dev. Lett., October 1987, pp. 496-498 both investigate the effect of such encroachment in vertical bipolar transistors similar to that of FIG. 1. Tang et al reports decreases in the transistor cutoff frequency f.sub.T and the small-signal transistor current gain. Cutoff frequency f.sub.T is the frequency at which the small-signal current gain drops to 1. Lu et al reports a decrease in the collector current I.sub.c.
An important parameter in bipolar transistor design is the punch-through voltage V.sub.p. This is the value of the collector-to-emitter voltage V.sub.CE at which the depletion region of the collector-base junction reaches the depletion region of the emitter-base junction when the base is open or when the base-to-emitter voltage V.sub.BE is at a selected value.
FIGS. 2a, 2b, 3a, and 3b are helpful in understanding the punch-through phenomenon. FIG. 2a illustrates a simplified one-dimensional version of an npn transistor during normal transistor operation, where t.sub.E and t.sub.B respectively are the emitter and base thicknesses. FIG. 3a illustrates the transistor when it is in the punch-through condition. FIGS. 2b and 3b respectively depict the potentials across the transistor when it is in the conditions of FIGS. 2a and 3a.
During normal operation, electrons in the emitter must overcome the potential barrier at the emitter-base junction in order to enter the quasi-neutral region of the base between the two depletion regions. Electrons then diffuse across the quasi-neutral region until they reach the collector-base depletion region where the electric field pulls them into the collector. See FIGS. 2a and 2b. Altogether, the current flow from emitter to collector is barrier limited and diffusion limited. The magnitude of collector-to-emitter voltage V.sub.CE does not substantially impact the magnitude of the emitter-to-collector current during normal operation because (a) the potential barrier at the emitter-base junction is controlled by the base-to-emitter voltage V.sub.BE and (b) the diffusion-limiting action on the emitter-to-collector current flow is determined by the thickness of the quasi-neutral region of the base.
When collector-to-emitter voltage V.sub.CE is raised to such a value that the collector-base depletion region punches through to the emitter-base depletion region, the quasi-neutral region of the base is eliminated as shown in FIGS. 3a and 3b. The diffusion limitation on the emitter-to-collector current flow is no longer present. Also, voltage V.sub.CE now directly influences the emitter-base barrier potential, causing its magnitude to be easily reduced. The net result is that the number of electrons passing through the base increases rapidly in a generally undesirable manner as voltage V.sub.CE is increased. Accordingly, it is desirable that the magnitude of punch-through voltage V.sub.P be high.
Another important bipolar design parameter is the Early voltage V.sub.A. At a given value of base-emitter voltage V.sub.BE , collector current I.sub.C is ideally independent of collector-to-emitter voltage V.sub.CE across the normal V.sub.CE operating range. However, because the size of the quasi-neutral region of the base decreases with increasing V.sub.CE, I.sub.C actually increases slowly with increasing V.sub.CE at fixed V.sub.BE in the manner generally shown in FIG. 4.
Early voltage V.sub.A is a transistor modeling parameter that constitutes the voltage at which the collector current asymptotes approximately intersect the V.sub.CE axis. The points at which the I.sub.C asymptotes at various V.sub.BE values intersect the V.sub.CE axis do not exactly coincide in a real bipolar transistor. Nonetheless, it has turned out to be a good modeling parameter to consider the I.sub.C asymptotes as all meeting at the V.sub.A position on the V.sub.CE axis. As with punch-through voltage V.sub.P, it is desirable that the magnitude of the Early voltage V.sub.A be high, ideally infinite.
A critical engineering trade-off relating to the intrinsic base involves punch-through voltage V.sub.P, Early voltage V.sub.A, and the base (series) resistance r.sub.B, on one hand, and cutoff frequency f.sub.T and collector current I.sub.c, on the other hand. Reducing base thickness t.sub.B and/or the total base doping causes f.sub.T and I.sub.C to increase. The current gain also increases with reduced t.sub.B. However, V.sub.P, V.sub.A, and r.sub.B are degraded when t.sub.B and/or the base doping is reduced.
In a simplified one-dimensional analysis, this trade-off can be seen from the following equations that apply to a symmetrical single-emitter vertical npn transistor such as that shown in FIG. 1: ##EQU1## where: x is an integrating variable in the base along the direction of main current flow,
.alpha..sub.O is the static common-base current gain (nearly 1), PA1 D.sub.n is the average electron diffusivity in the base, PA1 t.sub.B is the metallurgical thickness of the base--i.e., the distance between the emitter-base and collector-base junctions, _ PA1 t.sub.BEFF is the effective electrical thickness of the base--i.e., the distance between the boundaries of the emitter-base and collector-base depletion regions, PA1 n.sub.i is the intrinsic electron density (approximately 1.4.times.10.sup.10 electrons/cm.sup.3 in silicon at room temperature), PA1 N.sub.A is the base (acceptor) dopant concentration, PA1 W.sub.E is the lateral width of the emitter, PA1 L.sub.E is the length of the emitter, PA1 C.sub.jc is the depletion capacitance of the collector-base junction per unit area, PA1 N.sub.D is the collector (donor) dopant concentration, assumed to be constant and much smaller than base dopant concentration N.sub.A except in the immediate vicinity of the collector-base junction, PA1 .mu..sub.n, which equals D.sub.n q/kT, is the electron mobility, PA1 q is the electronic charge, PA1 k is Boltzmann's constant PA1 T is the absolute temperature, PA1 .epsilon..sub.O is the permittivity of free space, and PA1 K.sub.s is the relative permittivity of silicon. Use of t.sub.BEFF in the dopant integral (in each) of Eqs. 2 and 4 indicates that this integral is taken across the quasi-neutral region of the intrinsic base--i.e., the region extending between the two depletion regions. The dopant integral in Eqs. 2 and 4 is commonly referred to as the Gummel number. The dopant integral in Eqs. 3 and 5 is taken across the full metallurgical thickness of the base as indicated by the use of t.sub.B in this integral. Eqs. 1-4 are available in prior art semiconductor literature. See: (a) Philips, Transistor Engineering (McGraw-Hill; reprinted: Robert E. Krieger Pub. Co., 1981), 1962, pages 298-304; (b) Warner et al, Transistor Fundamentals for the Integrated-Circuit Engineer (John Wiley & Sons), 1983, pages 559-562; (c) Muller et al, Device Electronics for Integrated Circuits (John Wiley & Sons), 1977, pages 241-245; and (d) Grove, Physics and Technology of Semiconductor Devices (John Wiley & Sons), 1967, pages 228-230.
Eq. 5 has been derived here based on the following approximations: (a) the base region is totally depleted by the collector-base voltage at punch-through and (b) the collector-base junction is sufficiently asymmetrical to apply the single-sided abrupt approximation for the calculation of its depletion layer thickness, and to neglect the voltage drop on its heavily doped side. These modeling approximations are considered to be particularly valid in high-frequency transistors.
In particular, equating the depletion layer charges in the base and collector leads to: ##EQU2## where X.sub.dc is the total depletion thickness on the collector side of the collector-base junction. Assuming that X.sub.dC is approximately equal to the total depletion thickness along the collector-base junction according to classical pn-junction theory as provided in Grove (cited above), one has: ##EQU3## Substituting Eq. 7 into Eq. 6 produces Eq. 5.
If base dopant concentration N.sub.A is reduced, the dopant integral in Eq. 2 decreases along with t.sub.BEFF in Eq. 1. Collector current I.sub.C and cutoff frequency f.sub.T thereby increase, as is desirable. However, the dopant integrals in Eqs. 3-5 also decrease. This leads to decreases in punch-through voltage V.sub.P and Early voltage V.sub.A and an increase in base resistance r.sub.B, all of which are disadvantageous. It would be desirable to increase the collector current and cutoff frequency without degrading the punch-through voltage, Early voltage, and base resistance.